1. Field of the Invention
The present invention relates to a method for aligning a processed substrate, in an exposure apparatus, a repairing apparatus, an inspection apparatus or the like for producing semiconductor devices and liquid crystal display devices.
2. Related Background Art
In exposure apparatus for transferring circuit patterns of masks or reticles (hereinafter collectively called reticles) in superposed manner onto a semiconductor substrate (wafer) constituting the processed substrate, the reticle pattern and the semiconductor substrate have to be precisely aligned. Among such apparatus, there is frequently employed the exposure apparatus of so-called step-and-repeat type, which supports a semiconductor substrate on a two-dimensionally movable stage and repeats the steps of stepwise moving said semiconductor substrate by said stage and exposing said semiconductor substrate in succession to the circuit pattern of the reticle, and, in particular, such exposure apparatus of reduction production type, or so-called stepper, is commonly used.
In the following there will be outlined an aligning method for the semiconductor substrate, disclosed in the U.S. Pat. No. 4,780,617 and 4,833,621 and employed in the conventional steppers.
On the semiconductor substrate, there are formed plural chip patterns, including alignment marks and arranged regularly according to predetermined coordinates of arrangement. However, even when the semiconductor substrate is stepped according to the designed coordinate values, it is not necessarily exactly aligned to the exposure position, because of the following reasons:
(1) remaining rotational error .theta. of the semiconductor substrate; PA1 (2) orthogonality error w in the stage coordinate system (or in the shot arrangement); PA1 (3) linear elongation/contraction Rx, Ry of the semiconductor substrate.; and PA1 (4) offset (parallel displacement) Ox, Oy of the semiconductor substrate (center position).
The coordinate conversion of the semiconductor substrate based on these four error (or six parameters) can be described by first-order conversion equations.
Thus, for a semiconductor substrate on which plural chip patterns including alignment marks are regularly arranged, following first-order transformation model is defined for transforming the coordinate system (x, y) on said substrate into the coordinate system (X, Y) of the stage: ##EQU1##
The transformation parameters a-f in this model can be determined by the following minimum square approximation.
At first, from the plural chip patterns (shot areas) on the substrate, there are selected n shot areas (n being an integer satisfying n.gtoreq.3). The alignment marks (x.sub.1, y.sub.1), x.sub.2, y.sub.2), . . . , (x.sub.n, y.sub.n) respectively attached to said shot areas are used for the alignment to a predetermined reference position and the coordinate values (x.sub.M1, y.sub.M1), (x.sub.M2, y.sub.M2), . . . , (x.sub.Mn, y.sub.Mn) are measured. The difference (.DELTA.x, .DELTA.y) between the value (X.sub.i, Y.sub.i) obtained by substituting the coordinate values (x.sub.i, y.sub.i) (i=1, . . . , n) of the alignment marks of the selected shot areas into the equation (10 and the measured values (x.sub.Mi, y.sub.Mi) at the alignment is considered as the alignment error. Said alignment error .DELTA.x, .DELTA.y can be defined by the following equation: ##EQU2##
By partially differentiating this equation (2) with each of the parameters a-f and placing each partial differential equal to zero, there can be obtained simultaneous equations: ##EQU3## The parameters a-f can be determined by solving these simultaneous equations. Subsequently the coordinates of all the shot areas on the substrate can be calculated from the equation (1) and can be utilized for the alignment of each shot area.
If satisfactory approximation cannot be attained by the first-order transformation equation, the alignment of the semiconductor substrate can be executed: by a higher order equation: ##EQU4## The equation (4) is naturally reduced to the equation in case of N=1.
However, the semiconductor substrate to be processed on the stepper is often already subjected to a heat treatment as a part of the manufacturing process for the semiconductor device, and, for this reason, the chip patterns which are originally arranged in regular manner according to a predetermined coordinate system are sometimes so severely distorted as not be approximated by the first-order transformation equation, due to the elongation, contraction and deformation resulting from such thermal treatment. In such case it is difficult to attain a satisfactory precision of alignment over the entire substrate.
On the other hand, in the alignment utilizing a second- or higher-order transformation equation, the number of terms of such equation is larger than that in the first-order transformation. Consequently, in order to secure the sufficient precision of alignment, it becomes necessary to measure the coordinate values on a larger number of alignment marks than in the first-order transformation, so that the entire throughput of the apparatus has to be sacrificed.
Also in case some chip patterns alone on the substrate are significantly aberrated from the arrangement, the alignment utilizing first-order transformation equation is unable to exactly determine the coordinate of such arrangement. Stated differently, in case of a chip pattern including a significant non-linear error (particularly irregular non-linear error), a desired precision of alignment cannot be obtained, and the production yield is deteriorated because of formation of defective chips. In such situation, it is still difficult to attain the desired precision of alignment even with the application of a second- or higher-order transformation equation, and such application will deteriorate the throughput.